1. Field of the Invention
This invention relates to a level shifter that can output signals with increased voltage but at the same level, based on the input signal received. This invention specifically relates to a level shifter that receives a high level input signal and a low level input signal and then generate a high voltage output signal and a low voltage output signal simultaneously.
2. Description of the Prior Art
Level shifter is an important element which is used to shift the digital signals from one voltage to another voltage. Therefore, the level shifter is often disposed between two digital modules corresponding to two different interface voltages in order to convert the voltage of one signal generated by one digital module to a voltage that another digital module can process.
FIG. 1 is a circuit diagram illustrating a conventional level shifter 10. As FIG. 1 shows, the conventional level shifter 10 includes a first transistor 20, a second transistor 21, the third transistor 22, a fourth transistor 23, and an inverter 40, wherein the first transistor 20 and the second transistor 21 are P-Type Metal-Oxide-Semiconductor Field-Effect Transistors (PMOS-FETs). On the other hand, the third transistor 22 and the fourth transistor 23 are N-Type Metal-Oxide-Semiconductor Field-Effect Transistors (NMOS-FETs).
As FIG. 1 shows, the sources of both the first transistor 20 and the second transistor 21 are connected to the first voltage terminal Vp. In addition, the drains of both the first transistor 20 and the second transistor 21 are connected to the drains of the third transistor 22 and the fourth transistor 23. The gate of the first transistor 20 is connected to the drain of the second transistor 21. Similarly, the gate of the second transistor 21 is connected to the drain of the first transistor 20. Furthermore, the sources of the third transistor 22 and the fourth transistor 23 are both connected to a second voltage terminal Vn, wherein the first voltage terminal Vp and the second voltage terminal Vn establish the potential difference required by the conventional level shifter 10.
The first input terminal Vin1 of the conventional level shifter 10 accepts digital signals to be converted and then transmits the digital signal to the gate of the third transistor 22 in order to control the conduction of the third transistor 22. Furthermore, the inverter 40 will transmit a digital signal, whose polarity is opposite to that of the input digital signal, to the gate of the fourth transistor 23. In this way, when the voltage at the first input terminal Vin1 is logically high, the voltage at the second input terminal Vin2 will be logically low. Thus, the conventional level shifter 10 controls the first transistor 20, the second transistor 21, the third transistor 22, and the fourth transistor 23 based on the voltages of the first input terminal Vin1 and the second input terminal Vin2, so that the drains of the second transistor 21 and the fourth transistor 23 can output signals Vout whose voltages are higher than that at the first input terminal Vin1.
On the other hand, when the voltage at the first input terminal Vin1 is logically low, the voltage at the second input terminal Vin2 is logically high because the input terminal of the inverter 40 is connected to the first input terminal Vin1. This allows the conventional level shifter 10 to control the first transistor 20, the second transistor 21, the third transistor 22, and the fourth transistor 23 so that the conventional level shifter 10 can generate a logically low output signal Vout at the drains of the second transistor 21 and the fourth transistor 23, wherein the voltages of the input signal Vin1 and the output signal Vout are substantially equal to the voltage at the second voltage terminal Vn.
However, when the input signal Vin1 switches from logically high to logically low or from logically low to logically high, the voltage between the gate and the drain of the second transistor 21 and the voltage between the gate and the drain of the fourth transistor 23 will start seesawing with each other. Therefore, the conventional level shifter 10 needs to wait for the transistor to complete the conduction process before the output signal can switch between polarities. In this way, the time required by the conventional level shifter 10 illustrated in FIG. 1 to switch the polarity of the output signal may exceed specifications.
FIG. 2 is a circuit diagram illustrating another conventional level shifter 11. The conventional level shifter 11 illustrated in FIG. 2 further includes a fifth transistor 24 and a sixth transistor 25. The source and the drain of the fifth transistor 24 are connected to the drain of the first transistor 20 and the drain of the third transistor 22 respectively, wherein the gate of the first transistor 20 is connected to the drains of the fourth transistor 23 and the sixth transistor 25. Furthermore, the source and the drain of the sixth transistor 25 are connected to the drains of the second transistor 21 and the fourth transistor 23 respectively, wherein the gate of the second transistor 21 is connected to the drains of the third transistor 22 and the fifth transistor 24.
The operation of the conventional level shifters 10 illustrated in FIG. 1 and FIG. 2 are substantially the same. When the input signal at the first input terminal Vin1 is logically high, the drains of the fourth transistor 23 and the sixth transistor 25 will generate a logically high output signal Vout whose voltage is higher than the input voltage Vin1. On the other hand, when the voltage at the first input terminal Vin1 is logically low, a logically low output signal Vout will be generated at the drains of the fourth transistor 23 and the sixth transistor 25, wherein the voltage of the output signal is substantially equal to that at the second voltage terminal Vn.
Furthermore, as FIG. 2 shows, the gates of the fifth transistor 24 and the sixth transistor 25 both accept a bias signal VB that is used to increase the potential difference between the gate and the drain of the third transistor 22 as well as between the gate and the drain of the fourth transistor 23, in order to reduce the time for the output signal Vout to switch between polarities when the input signal Vin1 switches between polarities. However, the conventional level shifter 11 illustrated in FIG. 2 needs to provide an extra bias signal VB and therefore may consume more power compared with the conventional level shifter 10 illustrated in FIG. 1.
This shows that how to improve the transition speed of output signal Vout while reducing the power consumption is one of many important issues for the level shifter.